[Fwd: Support] [scilab-Users] Scicos Block with Different Output Port Types?
sorry for the first incomplete (untested) answer and the following
delay: we are very busy for the next Scilab 5 release (Scicos is
included, of course ;) .
Back to our business: please try the attached files. With this
interfacing function the compilation is OK. I double checked the
coherency trying to invert the output connections: a warning dialog box
about the data type and size appear.
Mission accomplished ? I don't think so.
To finish the job we need a "test.c" computational function for
simulation and a "set" section inside "TEST.sci" for a nice user's
By the way, the standard technique to write Scicos block is to begin
from an already working code of a similar block.
If you have specific request, we will be happy to help/guide you.